The present invention relates to a semiconductor apparatus such as a solid-state imaging apparatus, a method of manufacturing the same, a method of designing the same, and an electronic apparatus such as a camera having the solid-state imaging apparatus.
An amplification type solid-state imaging apparatus representatively including a MOS type image sensor such as complementary metal oxide semiconductor (CMOS) is known in the art as a solid-state imaging apparatus. A charge transmission type solid-state imaging apparatus representatively including a charge coupled device (CCD) image sensor is also known in the art. Such solid-state imaging apparatuses are widely used in a digital still camera, a digital video camera, or the like. Recently, as a solid-state imaging apparatus mounted in a mobile device such as a camera-equipped mobile phone or a personal digital assistant (PDA), the MOS type image sensor is widely used when taking a low power voltage, low power consumption, or the like into account.
The MOS type solid-state imaging apparatus includes a pixel array obtained by arranging a plurality of unit pixels in a 2-dimensional array (pixel area) and a peripheral circuit area, in which the unit pixel includes a photodiode functioning as a photoelectric conversion portion and a plurality of pixel transistors. A plurality of pixel transistors are formed from a MOS transistor, and a three-transistor structure including a transmission transistor, a reset transistor, and an amplification transistor, or a four-transistor structure additionally including a selection transistor are used.
In the related art, as one of the MOS type solid-state imaging apparatuses, various solid-state imaging apparatuses were proposed, in which a semiconductor chip including the pixel area where a plurality of pixels are arranged and a semiconductor chip including a logic circuit for performing signal processing are electrically connected and integrated as a single device. For example, Japanese Unexamined Patent Application Publication No. 2006-49361 discloses a semiconductor module in which a rear-surface illuminated type image sensor chip having a micropad in each pixel cell is connected to a signal processing chip having a signal processing circuit and a micropad using a microbump.
Japanese Unexamined Patent Application Publication No. 2007-13089 discloses a device obtained by mounting, on the interposer (intermediate substrate), a sensor chip as a rear-surface illuminated type MOS solid-state imaging element where an imaging pixel portion is provided and a signal processing chip including peripheral circuits for signal processing. In Japanese Unexamined Patent Application Publication No. 2008-130603, a configuration having an image sensor chip, a thin circuit substrate, and a logic circuit chip for signal processing are disclosed. In addition, the thin circuit substrate and the logic circuit chip are electrically connected to each other, and the thin circuit substrate is electrically connected from the rear surface of the image sensor chip through a through-hole via.
Japanese Patent Publication No. 4000507 discloses a solid-state imaging apparatus in which a through electrode is provided in the solid-state imaging element supported by a transparent substrate, and the solid-state imaging element is electrically connected to the flexible circuit substrate through the through electrode. In addition, Japanese Unexamined Patent Application Publication No. 2003-31785 discloses a rear-surface illuminated type solid-state imaging apparatus in which an electrode passing through the support substrate is provided.
As disclosed in Japanese Unexamined Patent Application Publication Nos. 2006-49361, 2007-13089, and 2008-130603, various techniques for integrating the image sensor chip with other kinds of circuit chips such as logic circuit have been proposed. In the related art, nearly completed functional chips are integrated into a single chip by forming a through-connection hole and vertically stacking chips while they can be connected to each other.
As recognized even in the aforementioned solid-state imaging apparatuses of the related art, constructing a semiconductor device by connecting together different kinds of stacked chips by way of a connection conductor passing through the substrate is known. However, since it is necessary to open the connection hole while insulation is secured in the deep or lower substrate, those techniques are impractical because they are not cost efficient in terms of the manufacturing process necessary for the processing of the connection hole and the bury the connection conductor.
Meanwhile, for example, it is necessary to perform thinning of the upper chip up to the limit in order to form a small contact hole of about 1 μm. In this case, the manufacturing process becomes complicated, and cost increases due to problems such as the necessity to attach an upper chip to the support substrate before the thinning. Furthermore, in order to bury the connection conductor in the connection hole having a high aspect ratio, it is necessary to use a CVD film having a high coatability such as tungsten (W) as the connection conductor so that a material of the connection conductor is limited.
In order to provide economic efficiency that can be conveniently applied to mass production, the inventors view it desirable to significantly reduce an aspect ratio of the connection hole to make it easy to manufacture and provide a technique of fabricating the connection hole using a wafer manufacturing process of the related art without using a special connection hole fabrication. In this case, depths are different between a contact hole connected to the upper chip and a contact hole passing through the upper chip and reaching the lower chip. However, it is preferable to perform formation through the same etching process or the same metal burying process if possible.
In addition, in the solid-state imaging apparatus or the like, it is desired to achieve high performance by forming the image area and the logic circuit for signal processing to exhibit sufficient performance.
Even in semiconductor apparatuses having other semiconductor integrated circuits without being limited to the solid-state imaging apparatus, it is desirable to achieve high performance by forming each semiconductor integrated circuit to exhibit sufficient performance.
On the other hand, if design is carried out such that necessary functions are separately included in each of the upper and lower chips, since the circuit areas of portions having common functions are overlapped, the chip size increases, and it is difficult to reduce costs. Therefore, in order to at least reduce cost, one might design the areas of portions having the same function between upper and lower chips to be commonly used to the maximum.